Stopwatch Design on a FPGA

Introduction

 This project involved creating a stopwatch using Verilog and implementing it on the DE10 Lite Board. The main goals were to design a clock divider, stopwatch logic, and seven-segment encoder, along with functional buttons (start/stop, reset, hold), six seven-segment displays, and indicator LEDs. The project deepened my understanding of FPGA capabilities, primitive gates, testbenches, debugging, and binary to BCD/hex encoders.

Design and Development 

1. Clock Divider Module: A clock divider was designed to reduce a 50 MHz clock signal to 100 Hz using a 16-bit binary counter. Both structural and behavioral logic were employed to achieve the frequency division, with the counter toggling once it reached a preset value.

2. Stopwatch Logic Module: This module implemented the stopwatch, counting in tenths of seconds, seconds, and minutes. It used inputs like the clock signal, reset, start/stop, and hold buttons. The stopwatch increments time values until reaching predefined limits, then resets, with an overflow flag signaling when the max time is reached.

3. Binary to Seven Segment Encoder: This module converts binary inputs into seven-segment hex values by first encoding them into Binary Coded Decimal (BCD). The structural logic connects the BCD encoders to hex encoders, which drive the seven-segment displays.

4. Top-Level Stopwatch Entity: The top-level stopwatch integrates all submodules: clock divider, stopwatch logic, and seven-segment encoder. It manages signal flow for clock, control signals, and time data while ensuring proper visualization on the seven-segment displays.

Validation: Testbenches were created for all modules (BCDEncoder, HexEncoder, SevenSegEncoder, ClockDivider, and StopwatchLogic) to validate their functionality. Each module performed correctly under different test cases, confirming proper operation.

Conclusions and Reflections

 The project challenged my approach to design and coding, especially when integrating modules. Debugging module interconnections was a major hurdle. Although I couldn't fully implement the stopwatch on the DE10 Lite board, this project helped me improve my problem-solving and logical thinking skills. Given more time, I would refine the StopwatchLogic for better efficiency and add functionality like time snapshots for enhanced usability.